Novel Frequency Doubler Circuits and Dividers Using Duty Cycle Control Buffers

Novel frequency doubler circuits and dividers for clock signal generation are presented. In combination with two edge detectors and two duty cycle control buffers a low cost frequency doubler circuit is achieved as compared to Phase-Locked Loop (PLL) design. An input clock signal with an unpredictable duty cycle is inputted to a rising (or falling) edge detector. The edge detector converts the positive (or negative) transitions to a one shot pulse train whose frequency is the same as that of the input clock. However, the one shot pulse train has its duty cycle far less than 50%. By a first 50% duty cycle control buffer the output waveform of the resulted clock signal is symmetrical. The output of the first-stage duty cycle buffer is then edge detected by a rising and falling edge detector, so that the resulted one shot pulse train has twice the frequency of the incoming 50% duty cycle signal. Finally, the second one shot signals are duty cycle adjusted in the second-stage duty cycle control buffer, to restore its 50% duty cycle. Therefore, two times frequency multiplication is achieved with low cost as compared to Phase-Locked Loop (PLL) design. Furthermore, a novel design approach for frequency dividers using duty cycle control circuit is also demonstrated. Simulation results for both frequency multiplication and division confirm the validity of the proposed design approach. Key-Words: Frequency doubler, Dividers, Phase-locked loop, Duty cycle, XOR, Edge detector